View MH16M40AJD-6_1278913.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Preliminary Spec.
Some of contents are subject to change without notice.
MITSUBISHI LSIs
MH16M40AJD -6
Proto-2
FAST PAGE MODE ( 16,777,216-WORD BY 40-BIT ) DYNAMIC RAM
DESCRIPTION
The MH16M40AJD is a 16M word by 40-bit dynamic RAM module and consists of 10 industry standard 16M X 4 dynamic RAMs in a TSOP package. The ICs are mounted on both sides of two small PC boards (Ceracom) with the flash gold plating and form a convenient 69-pin WDIP package.
PIN CONFIGURATION ( TOP VIEW )
FEATURES
Type name RAS CAS access access time time (max.ns) (max.ns) Address OE Cycle Power access access dissipatime time time tion (max.ns) (max.ns) (min.ns) (typ.mW)
MH16M40AJD-6
60
15
30
15
110
2500
Utilizes industry standard 16M X 4 DRAMs in TSOP package Low stand-by power dissipation 13mW (Max) ............................ CMOS lnput level Low operating power dissipation MH16M40AJD - 6 ........................ 3242 mW (Max) Fast-page mode , Read-modify-write,RAS-only refresh CAS before RAS refresh, Hidden refresh capabilities Early-write mode and OE to control output buffer impedance All inputs, output TTL compatible and low capacitance 4096 refresh cycles every 64ms (A0 - A12) (CbR only) Includes (0.22uF x 12) decoupling capacitors 5.0V 5% Vcc 3.3V Vdd by onboard mounted regulators TTL input converted to LVTTL by onboard mounted level shifters.
DQ1 1 DQ2 2 DQ3 3 DQ4 4 DQ5 5 DQ6 6 Vss 7 DQ7 8 DQ8 9 DQ9 10 DQ10 11 DQ11 12 DQ12 DQ13 Vcc DQ14 /CAS0 /RAS0 DQ15 DQ16 DQ17 /W0 NC DQ18 DQ19 Vss DQ20 A0 A1 A2 A3 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
APPLICATION
Main memory unit for computers, Microcomputer memory, Refresh memory for CRT
PIN DESCRIPTION
Pin Name A0-A12 RAS 0 CAS 0 W0 OE 0 Vcc Vss Function Address Inputs Row Address Strobe Input Column Address Strobe Input Write Control Input Output Enable Input Power Supply (+5V) Ground (0V)
DQ1-DQ40 Data Inputs / Outputs
A4 32 A5 33 A6 34
69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35
Key Pin Vss DQ40 DQ39 DQ38 DQ37 DQ36 Vcc DQ35 DQ34 DQ33 DQ32 DQ31 DQ30 DQ29 Vss DQ28 NC NC DQ27 DQ26 DQ25 /OE0 NC DQ24 DQ23 Vcc DQ22 DQ21 A12 A11 A10 A9 A8 A7
MIT - DS - 0069 -1.1
MITSUBISHI ELECTRIC ( 1 / 17 )
31/ Jan./1997
Preliminary Spec.
Some of contents are subject to change without notice.
MITSUBISHI LSIs
MH16M40AJD -6
Proto-2
a number of other functions, e.g., fast page mode, CAS before RAS refresh, and delayed-write. The input conditions for each are shown in Table 1.
FAST PAGE MODE ( 16,777,216-WORD BY 40-BIT ) DYNAMIC RAM
FUNCTION
The MH16M40AJD provide, in addition to normal read, write, and read-modify-write operations,
Table 1 Input conditions for each mode
Inputs Operation RAS Read Write (Early write) Write (Delayed write) Read-modify-write Hidden refresh CAS before RAS refresh Standby ACT ACT ACT ACT ACT ACT NAC CAS ACT ACT ACT ACT ACT ACT DNC W NAC ACT ACT ACT NAC NAC DNC OE ACT DNC DNC ACT ACT DNC DNC Row address APD APD APD APD DNC DNC DNC Column address APD APD APD APD DNC DNC DNC Input/Output Refresh Input OPN VLD VLD VLD OPN DNC DNC Output VLD OPN IVD VLD VLD OPN OPN YES YES YES YES YES YES NO Fast page mode identical Remark
Note : ACT : active, NAC : nonactive, DNC : don' t care, VLD : valid, IVD : Invalid,APD : applied, OPN : open
BLOCK DIAGRAM
28,29,30,31,32,33,34,35,36,37,38,39,40 Add /W0 /OE0 /CAS0 /RAS0 22 47 17 18 SN74CBT3384 RAS CAS OE W Add M5M467400ATP RAS CAS OE W Add M5M467400ATP RAS CAS OE W Add M5M467400ATP RAS CAS OE W Add M5M467400ATP RAS CAS OE W Add M5M467400ATP RAS CAS OE W Add M5M467400ATP RAS CAS OE W Add M5M467400ATP Voltage regulator 15 43 Vcc 62 RAS CAS OE W Add 7 Vss 26 54 68 RAS CAS OE W Add M5M467400ATP C1 to C12 0.22 uF M5M467400ATP 59 60 61 63 64 65 66 67 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 LT1117C ST-3.3 RAS CAS OE W Add M5M467400ATP SN74CBT3384 1 2 3 4 5 6 8 9 10 11 12 13 14 16 19 20 21 24 25 27 41 42 44 45 48 49 50 53 55 56 57 58 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32
MIT - DS - 0069 -1.1
MITSUBISHI ELECTRIC ( 2 / 17 )
31/ Jan./1997
Preliminary Spec.
Some of contents are subject to change without notice.
MITSUBISHI LSIs
MH16M40AJD -6
Proto-2
Conditions Ratings -0.5 ~ 7 -0.5 ~ 6 -0.5 ~ 6 50 Unit V V V mA W C C
FAST PAGE MODE ( 16,777,216-WORD BY 40-BIT ) DYNAMIC RAM
ABSOLUTE MAXIMUM RATINGS
Symbol Vcc VI V0 I0 Pd Topr Tstg Supply voltage Input voltage Output voltage Output current Power dissipation Operating temperature Storage temperature Ta=25 C With respect to Vss Parameter
15 0 ~ 70 -40 ~ 100
RECOMMENDED OPERATING CONDITIONS
Symbol Vcc Vss VIH VIL Supply voltage Supply voltage High-level input voltage, all inputs Low-level input voltage, all inputs Parameter
(Ta=0 ~ 70 C , unless otherwise noted) (Note 1) Limits Unit V V V V
Min 4.75 0 2.0 -0.3
Nom 5 0
Max 5.25 0 5.5 0.8
Note 1 : All voltage values are with respect to Vss
ELECTRICAL CHARACTERISTICS
Symbol VOH VOL IOZ II ICC1 (AV) Parameter High-level output voltage Low-level output voltage Off-state output current Input current Average supply current from Vcc operating (Note 3,4) Supply current from Vcc , stand-by Average supply current from Vcc Fast-Page-Mode (Note 3,4) Average supply current from Vcc CAS before RAS refresh mode (Note 3)
(Ta=0 ~ 70 C , Vcc=5V 5%, Vss=0V, unless otherwise noted) (Note 2) Test conditions IOH=-2mA IOL=2mA
VII VII
Limits Min 2.4 0 Typ Max 3.6 0.4 10 5 900 10 5.4 800
Unit V V uA uA mA
Q floating 0V
VII VII
VOUT 3.6V
-10 -5
0V
VIN
5.25V, Other inputs pins=0V
RAS, CAS cycling tRC=tWC=min. output open RAS= CAS =VIH, output open RAS= CAS
IIV
ICC2
Vcc -0.2
mA
ICC4(AV)
RAS=VIL, CAS cycling tPC=min. output open CAS before RAS refresh cycling tRC=min. output open
mA
ICC6(AV)
1200
mA
Note 2: Current flowing into an IC is positive, out is negative. 3: Icc1 (AV), Icc4 (AV) and Icc6 (AV) are dependent on cycle rate. Maximum current is measured at the fastest cycle rate. 4: Icc1 (AV) and Icc4 (AV) are dependent on output loading. Specified values are obtained with the output open.
CAPACITANCE
Symbol CI (A) CI (OE) CI (W) CI (RAS) CI (CAS) CI / O
(Ta=0 ~ 70 C , Vcc=5V 5%, Vss=0V, unless otherwise noted) Parameter Test conditions Limits Min Typ Max 20 VI=Vss f=1MHZ Vi=25mVrms 20 20 20 20 20 Unit pF pF pF pF pF pF
Input capacitance, address inputs Input capacitance, OE input Input capacitance, write control input Input capacitance, RAS input Input capacitance, CAS input Input/Output capacitance, data ports
MIT - DS - 0069 -1.1
MITSUBISHI ELECTRIC (3 / 17 )
31/ Jan./1997
Preliminary Spec.
Some of contents are subject to change without notice.
MITSUBISHI LSIs
MH16M40AJD -6
Proto-2
Limits -6 Min Max 15 60 30 35 15 5 0 0 15 15 ns ns ns ns ns ns ns ns
FAST PAGE MODE ( 16,777,216-WORD BY 40-BIT ) DYNAMIC RAM
SWITCHING CHARACTERISTICS
Symbol tCAC tRAC tAA tCPA tOEA tCLZ tOFF tOEZ Parameter Access time from CAS Access time from RAS Columu address access time Access time from CAS precharge (Note 6,7) (Note 6,8) (Note 6,9) (Note 6,10) (Ta=0 ~ 70 C , Vcc=5V 5%, Vss=0V, unless otherwise noted , see notes 5,12,13)
Unit
(Note 6) Access time from OE Output low impedance time from CAS low (Note 6) Output disable time after CAS high Output disable time after OE high (Note 11) (Note 11)
Note 5: An initial pause of 500 us is required after power-up followed by a minimum of eight initialization cycles (any combination of cycles containing CAS before RAS refresh). Note the RAS may be cycled during the initial pause . And any 8 RAS or RAS/CAS cycles are required after prolonged periods (greater than 64 ms) of RAS inactivity before proper device operation is achieved. 6: Measured with a load circuit equivalent to 1TTL loads and 100pF.The reference levels for measuring of output signals are 2.0V(VOH) and 0.8V(VOL). 7: Assumes that tRCD tRCD(max) and tASC tASC(max). 8: Assumes that tRCD tRCD(max) and tRAD tRAD(max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, tRAC will increase by amount that tRCD exceeds the value shown. 9: Assumes that tRAD tRAD(max) and tASC tASC(max). 10: Assumes that tCP tCP(max) and tASC tASC(max). 11: tOFF(max) and tOEZ (max) defines the time at which the output achieves the high impedance state (IOUT I 10 uAI) and is not reference to VOH(min) or VOL(max).
IIV IIV IIV IIV
TIMING REQUIREMENTS (For Read, Write, Read-Modify-Write ,Refresh, and Fast-Page Mode Cycles)
(Ta=0 ~ 70 C , Vcc=5V 5%, Vss=0V, unless otherwise noted See notes 12,13) Limits Symbol tREF tRP tRCD tCRP tRPC tCPN tRAD tASR tASC tRAH tCAH tDZC tDZO tCDD tODD tT Refresh cycle time RAS high pulse width Delay time, RAS low to CAS low Delay time, CAS high to RAS low Delay time, RAS high to CAS low CAS high pulse width
Column address delay time from RAS low
Row address setup time before RAS low
Column address setup time before CAS low
Row address hold time after RAS low Column address hold time after CAS low Delay time, data to CAS low Delay time, data to OE low Delay time, CAS high to data Delay time, OE high to data Transition time (Note17) (Note17) (Note18) (Note18) (Note19)
Note 12: The timing requirements are assumed tT =5ns. 13: VIH(min) and VIL(max) are reference levels for measuring timing of input signals. 14: tRCD(max) is specified as a reference point only. If tRCD is less than tRCD(max), access time is tRAC. If tRCD is greater than tRCD(max), access time is controlled exclusively by tCAC or tAA. tRCD(min) is specified as tRCD(min) =tRAH(min) +2tH+tASC(min). 15: tRAD(max) is specified as a reference point only. If tRAD tRAD(max) and tASC tASC(max), access time is controlled exclusively by tAA. 16: tASC(max) is specified as a reference point only. If tRCD tRCD(max) and tASC tASC(max), access time is controlled exclusively by tCAC. 17: Either tDZC or tDZO must be satisfied. 18: Either tCDD or tODD must be satisfied. 19: tT is measured between VIH(min) and VIL(max).
IIV IIV IIV VII
MIT - DS - 0069 -1.1
VII
VII
VII
VII
VII
Parameter Min 40 (Note14) 20 10 0 10 (Note15) (Note16) 15 0 0 10 15 0 0 15 15 1
-6 Max 64 45
Unit ms ns ns ns ns ns 30 10 ns ns ns ns ns ns ns ns ns 50 ns
MITSUBISHI ELECTRIC (4 / 17 )
31/ Jan./1997
Preliminary Spec.
Some of contents are subject to change without notice.
MITSUBISHI LSIs
MH16M40AJD -6
Proto-2
FAST PAGE MODE ( 16,777,216-WORD BY 40-BIT ) DYNAMIC RAM
Read and Refresh Cycles
Limits Symbol tRC tRAS tCAS tCSH tRSH tRCS tRCH tRRH tRAL tOCH tORH Read cycle time RAS iow pulse width CAS iow pulse width CAS hold time after RAS iow RAS hold time after CAS iow Read Setup time after CAS high Read hold time after CAS iow Read hold time after RAS iow Column address to RAS hold time CAS hold time after OE iow RAS hold time after OE iow (Note 20) (Note 20) Parameter Min 110 60 15 60 15 0 0 10 30 15 15 -6 Max ns 10000 10000 ns ns ns ns ns ns ns ns ns ns Unit
Note 20: Either tRCH or tRRH must be satisfied for a read cycle.
Write Cycle (Early Write and Delayed Write)
Limits Symbol tWC tRAS tCAS tCSH tRSH tWCS tWCH tCWL tRWL tWP tDS tDH tOEH Write cycle time RAS iow pulse width CAS iow pulse width CAS hold time after RAS iow RAS hold time after CAS iow Write setup time before CAS low Write hold time after CAS iow CAS hold time after W iow RAS hold time after W iow Write pulse width Data setup time before CAS iow or W iow Data hold time after CAS iow or W iow OE hold time after W iow (Note 22) Parameter Min 110 60 15 60 15 0 10 15 15 10 0 10 15 10000 10000 -6 Max ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
MIT - DS - 0069 -1.1
MITSUBISHI ELECTRIC ( 5 / 17 )
31/ Jan./1997
Preliminary Spec.
Some of contents are subject to change without notice.
MITSUBISHI LSIs
MH16M40AJD -6
Proto-2
FAST PAGE MODE ( 16,777,216-WORD BY 40-BIT ) DYNAMIC RAM
Read-Write and Read-Modify-Write Cycles
Limits Symbol tRWC tRAS tCAS tCSH tRSH tRCS tCWD tRWD tAWD tCWL tRWL tWP tDS tDH tOEH Parameter Min Read write/read modify write cycle time RAS low pulse width CAS low pulse width CAS hold time after RAS low RAS hold time after CAS low Read setup time before CAS low Delay time, CAS low to W low Delay time, RAS low to W low Delay time, address to W low CAS hold time after W low RAS hold time after W low Write pulse width Data setup time before W low AU Data hold time after W low AO OE hold time after W low AU AO (Note22) (Note22) (Note22) (Note21) 150 95 50 95 50 0 30 75 45 15 15 10 0 10 15
IIV
-6 Max
Unit ns 10000 10000 ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Note 21: tRWC is specified as tRWC(min)=tRAC(max)+tODD(min)+tRWL(min)+tRP(min)+4tT. 22: tWCS, tCWD,tRWD and tAWD and,tCPWD are specified as reference points only. If tWCS tWCS(min) the cycle is an early write cycle and the DQ pins will remain high impedance throughout the entire cycle. If tCWD tCWD(min), tRWD tRWD (min), tAWD tAWD(min) and tCPWD tCPWD(min) (for fast page mode cycle only), the cycle is a read-modify-write cycle and the DQ will contain the data read from the selected address. If neither of the above condition (delayed write) of the DQ (at access time and until CAS or OE goes back to VIH ) is indeterminate.
IIV IIV
Fast-Page Mode Cycle (Read, Early Write, Read -Write, Read-Modify-Write Cycle)
Limits Symbol tPC tPRWC tRAS tCP tCPRH tCPWD Parameter Min Fast page mode read/write cycle time
Fast page mode read write/read modify write cycle time
IIV
(Note 23)
-6 Max 40 75 100 10 35 (Note22) 35 102400 15
Unit ns ns ns ns ns ns
RAS iow pulse width for read write cycle (Note24) CAS high pulse width RAS hold time after CAS precharge Delay time, CAS precharge to W iow (Note25)
CAS before RAS Refresh Cycle
Symbol tCSR tCHR tRSR tRHR Parameter
(Note 26) Limits -6 Min Max ns ns ns ns 10 10 10 10 Unit
CAS setup time before RAS low CAS hold time after RAS low Read setup time before RAS low Read hold time after RAS low
Note 26: Eight or more CAS before RAS cycles instead of eight RAS cycles are necessary for proper operation of CAS before RAS refresh mode.
MIT - DS - 0069 -1.1
IIV
Note 23: All previously specified timing requirements and switching characteristics are applicable to their respective fast page mode cycle. 24: tRAS(min) is specified as two cycles of CAS input are performed. 25: tCP(max) is specified as a reference point only. If tCP tCP(max),access time is controlled exclusively by tCAC.
MITSUBISHI ELECTRIC (6 / 17 )
31/ Jan./1997
IIV
Preliminary Spec.
Some of contents are subject to change without notice.
MITSUBISHI LSIs
MH16M40AJD -6
Proto-2
FAST PAGE MODE ( 16,777,216-WORD BY 40-BIT ) DYNAMIC RAM
Timing Diagrams Read Cycle
(Note 27)
tRC tRAS VIH VIL tCSH tCRP VIH VIL tASR VIH VIL tRAD tRAH tASC tCAH
COLUMN ADDRESS
tRP
RAS
tRCD
tRSH tCAS
tRPC
tCRP
CAS
tRAL tCPN
tASR
A0 - 12
ROW ADDRESS
ROW ADDRESS
tRRH tRCS W VIH VIL tDZC VIH Hi-Z VIL tCAC tAA tCLZ VOH DQ (OUTPUTS) VOL Hi-Z tRAC tDZO VIH VIL tOEA tOCH tOFF tCDD tRCH
DQ (INPUTS)
DATA VALID
Hi-Z
tOEZ tODD
OE
Note 27
Indicates the don't care input. VIH(min) VIN VIH(max) or VIL(min) VIN VIL(max) Indicates the invalid output.
VII VII VII VII
MIT - DS - 0069 -1.1
MITSUBISHI ELECTRIC (7 / 17 )
31/ Jan./1997
Preliminary Spec.
Some of contents are subject to change without notice.
MITSUBISHI LSIs
MH16M40AJD -6
Proto-2
FAST PAGE MODE ( 16,777,216-WORD BY 40-BIT ) DYNAMIC RAM
Write Cycle (Early write)
tWC tRAS VIH VIL tCSH tCRP VIH VIL tASR VIH VIL tASR tRAH tASC tCAH
COLUMN ADDRESS ROW ADDRESS
tRP
RAS
tRCD
tRSH tCAS
tRPC
tCRP
CAS
A0 - A12
ROW ADDRESS
tWCS W VIH VIL tDS VIH
tWCH
tDH
DQ (INPUTS)
DATA VALID
VIL
VOH DQ (OUTPUTS) VOL
Hi-Z
OE
VIH VIL
MIT - DS - 0069 -1.1
MITSUBISHI ELECTRIC (8 / 17 )
31/ Jan./1997
Preliminary Spec.
Some of contents are subject to change without notice.
MITSUBISHI LSIs
MH16M40AJD -6
Proto-2
FAST PAGE MODE ( 16,777,216-WORD BY 40-BIT ) DYNAMIC RAM
Write Cycle (Delayed write)
tWC tRAS VIH VIL tCSH tCRP VIH VIL tASR tRAH tASC tCAH tASR
ROW ADDRESS
tRP
RAS
tRCD
tRSH tCAS
tRPC
tCRP
CAS
VIH A0 - A12 VIL
ROW ADDRESS
COLUMN ADDRESS
tCWL tRCS W VIH VIL tWCH tDZC DQ (INPUTS) VIH VIL tCLZ Hi-Z tDS tDH
DATA VALID
tRWL tWP
VOH DQ (OUTPUTS) VOL
Hi-Z tOEZ tODD tOEH
Hi-Z
tDZO VIH VIL
OE
MIT - DS - 0069 -1.1
MITSUBISHI ELECTRIC ( 9 / 17 )
31/ Jan./1997
Preliminary Spec.
Some of contents are subject to change without notice.
MITSUBISHI LSIs
MH16M40AJD -6
Proto-2
FAST PAGE MODE ( 16,777,216-WORD BY 40-BIT ) DYNAMIC RAM
Read-Write, Read-Modify-Write Cycle
tRWC tRAS VIH VIL tCSH tCRP CAS VIH VIL tASR tRAH tRAD tASC tCAH tASR tRCD tRSH tCAS tRPC tCRP tRP
RAS
VIH A0 - A12 VIL
ROW ADDRESS
COLUMN ADDRESS
ROW ADDRESS
tRCS VIH VIL
tAWD tCWD tRWD
tCWL tRWL tWP
W
tDS tDZC VIH DQ (INPUTS) VIL Hi-Z tCAC tAA tCLZ VOH DQ (OUTPUTS) VOL Hi-Z tRAC tDZO VIH VIL tOEA
DATA VALID
tDH
DATA VALID
Hi-Z tODD tOEZ tOEH
OE
MIT - DS - 0069 -1.1
MITSUBISHI ELECTRIC
10 ( / 17 )
31/ Jan./1997
Preliminary Spec.
Some of contents are subject to change without notice.
MITSUBISHI LSIs
MH16M40AJD -6
Proto-2
FAST PAGE MODE ( 16,777,216-WORD BY 40-BIT ) DYNAMIC RAM
CAS before RAS Refresh Cycle
tRC tRP RAS VIH VIL tCSR tRPC tCSR tRAS tRAS
tRC tRP
tRPC CAS VIH VIL
tCHR
tCHR
tRPC
tCRP
tCPN tASR VIH A0 - A12 VIL tRCH tRSR W VIH VIL tRHR tRSR tRHR
ROW ADDRESS COLUMN ADDRESS
tRCS
DQ (INPUTS)
VIH VIL tOFF
DQ (OUTPUTS)
VOH VOL tOEZ VIH
Hi-Z
OE VIL
MIT - DS - 0069 -1.1
MITSUBISHI ELECTRIC ( / 17 ) 11
31/ Jan./1997
Preliminary Spec.
Some of contents are subject to change without notice.
MITSUBISHI LSIs
MH16M40AJD -6
Proto-2
FAST PAGE MODE ( 16,777,216-WORD BY 40-BIT ) DYNAMIC RAM Hidden Refresh Cycle (Read)
(Note 28)
tRC tRAS RAS VIH VIL tCRP VIH VIL tRAD tASR A0 - A12 VIH VIL tRAH
ROW ADDRESS
tRC tRP tRAS tRP
tRCD
tRSH
tCHR
CAS
tASC
tCAH
COLUMN ADDRESS
tASR
ROW ADDRESS
tRCS tRAL VIH VIL tDZC tCDD tRRH
W
DQ (INPUTS)
VIH VIL tCAC tAA tCLZ Hi-Z tRAC tDZO VIL
Hi-Z
tOFF
VOH DQ (OUTPUTS) VOL
DATA VALID
Hi-Z tOEZ
tOEA tORH
tODD
W
VIH
Note 28: Early write, delayed write, read write or read modify write cycle is applicable instead of read cycle. Timing requirements and output state are the same as that of each cycle shown above.
MIT - DS - 0069 -1.1
MITSUBISHI ELECTRIC ( / 17 ) 12
31/ Jan./1997
Preliminary Spec.
Some of contents are subject to change without notice.
MITSUBISHI LSIs
MH16M40AJD -6
Proto-2
FAST PAGE MODE ( 16,777,216-WORD BY 40-BIT ) DYNAMIC RAM
Fast Page Mode Read Cycle
tRAS VIH VIL tCSH tCRP VIH VIL tRAD tASR VIH VIL tRAH tASC tCAH tASC tCAH tCPRH tASC tCAH tRCD tCAS tCP tPC tCAS tCP tRSH tCAS
tRP
RAS
CAS
tASR
ROW ADDRESS
A0 - A12
ROW ADDRESS
COLUMN-1
COLUMN-2
COLUMN-3
tRAL tRCS VIH VIL tDZC tDZC tDZC tRCH tRCS tRCH tRCS tRRH
tRCH
W
tCDD
VIH DQ (INPUTS) VIL
Hi-Z tCAC tAA tCLZ tOFF tAA
Hi-Z tCAC tCLZ
DATA VALID-1 DATA VALID-2
tOFF
tCAC tAA tCLZ
tOFF
VOH DQ (OUTPUTS) VOL
Hi-Z tRAC tDZO
DATA VALID-3
tCPA tOEA tOCH tOEZ tOEA tOCH
tCPA tOEZ tOEA tOCH tOEZ
VIL OE VIH tDZO tODD tODD tDZO tORH tODD
MIT - DS - 0069 -1.1
MITSUBISHI ELECTRIC ( / 17 ) 13
31/ Jan./1997
Preliminary Spec.
Some of contents are subject to change without notice.
MITSUBISHI LSIs
MH16M40AJD -6
Proto-2
FAST PAGE MODE ( 16,777,216-WORD BY 40-BIT ) DYNAMIC RAM
Fast Page Mode Write Cycle (Early Write)
tRAS VIH VIL tCSH tCRP VIH VIL tASR tRAH tASC tCAH tASC tCAH tASC tCAH tRCD tCAS tCP tPC tCAS tCP tRSH tCAS
tRP
RAS
CAS
tASR
ROW ADDRESS
A0 - A12
VIH VIL
ROW ADDRESS
COLUMN-1
COLUMN-2
COLUMN-3
tWCS W VIH VIL tDS VIH DQ (INPUTS) VIL
tWCH
tWCS
tWCH
tWCS
tWCH
tDH
DATA VALID-1
tDS
tDH
tDS
tDH
DATA VALID-3
DATA VALID-2
VOH DQ (OUTPUTS) VOL
Hi-Z
VIH OE VIL
MIT - DS - 0069 -1.1
MITSUBISHI ELECTRIC
14 / 17 ) (
31/ Jan./1997
Preliminary Spec.
Some of contents are subject to change without notice.
MITSUBISHI LSIs
MH16M40AJD -6
Proto-2
FAST PAGE MODE ( 16,777,216-WORD BY 40-BIT ) DYNAMIC RAM
Fast-Page Mode Write Cycle (Delayed Write)
tRAS VIH VIL tCSH tCRP VIH VIL tASR tRAH tASC tCAH tASC tCAH tRWL tCWL tRCD tCAS tCP CAS tRSH tPC tCAS
tRP
RAS
tASR
ROW ADDRESS
A0 - A12
VIH VIL
ROW ADDRESS
COLUMN-1
COLUMN-2
tRCS VIH VIL tWCH tDZC VIH DQ (INPUTS) VIL tDS Hi-Z
tCWL tWP
tRCS tWP
W
tWCH tDH
DATA VALID-1
tDZC tDS Hi-Z
tDH
DATA VALID-2
tCLZ VOH DQ (OUTPUTS) VOL Hi-Z tOEZ tODD tDZO Hi-Z
tCLZ Hi-Z tOEZ tODD tOEH
tDZO VIH OE VIL
MIT - DS - 0069 -1.1
MITSUBISHI ELECTRIC (15 / 17 )
31/ Jan./1997
Preliminary Spec.
Some of contents are subject to change without notice.
MITSUBISHI LSIs
MH16M40AJD -6
Proto-2
FAST PAGE MODE ( 16,777,216-WORD BY 40-BIT ) DYNAMIC RAM Fast Page Mode Read-Write,Read-Modify-Write Cycle
tRAS VIH VIL tCSH tCRP VIH VIL tASR tRAD tRAH tASC tCAH tASC tCAH tCWL tRCD tCAS tCP CAS tPRWC tCAS
tRP
RAS
tRWL
tASR
ROW ADDRESS
A0 - A12
VIH VIL
ROW ADDRESS
COLUMN-1
COLUMN-2
tAWD tRCS VIH VIL tRWD tDZC VIH DQ (INPUTS) VIL tDS Hi-Z tCAC tAA tCLZ DQ (OUTPUTS) VOH Hi-Z VOL tRAC tDZO VIH OE VIL tOEA
DATA VALID-1
tAWD tCWL tWP tRCS tCWD tWP
tCWD
W
tCPWD tDH
DATA VALID-1
tDZC tDS Hi-Z tCAC tAA tCLZ
tDH
DATA VALID-2
Hi-Z tODD tOEZ tDZO tOEA tCPA
DATA VALID-1
Hi-Z tODD tOEZ tOEH
MIT - DS - 0069 -1.1
MITSUBISHI ELECTRIC (16 / 17 )
31/ Jan./1997
Preliminary Spec.
Some of contents are subject to change without notice.
MITSUBISHI LSIs
MH16M40AJD -6
Proto-2
3.76
FAST PAGE MODE ( 16,777,216-WORD BY 40-BIT ) DYNAMIC RAM
23.39
1.22
0.5 2.54
PR
1.4
34X2.54=86.36
33X2.54=83.82
91.34
EL
IM
11MAX
IN
5.4MAX
AR
Y
3.1
0.25 5.4MAX
16.64 20.49
MIT - DS - 0069 -1.1
MITSUBISHI ELECTRIC (17 / 17 )
31/ Jan./1997

▲Up To Search▲

Price & Availability of MH16M40AJD-6

	To Download MH16M40AJD-6 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .